求一段用verilog写的lcd12864驱动程序，不能用的不给分~~
的有关信息介绍如下：
module xianshi(input sys_clk,input clr_n,//input key2,//input [11:0] buffer,output wire en,output reg rs,output wire rw,output reg [7:0] data,input key1,input key2);reg [16:0] count;reg clk ;reg f;reg [3:0] buffer_bit;reg [7:0] state;reg [15:0] buffer;wire key_val_1;wire key_val_2;assign en=clk;assign rw=0;parameter jiben=8'b00000000, xianshi=8'b00000001, qingchu=8'b00000010, dizhi1=8'b00000011, duanyu1=8'b00000100, idle=8'b00000101;always @(posedge sys_clk or negedge clr_n) begin if(clr_n==1'b0) count<=17'b0; else begin count<=count+17'b1; if(count==17'b0) begin clk<=~clk;end else ; endendalways@(posedge en or negedge clr_n )begin if(!clr_n) begin f<=0; state<=jiben; buffer_bit<=0; end else begin if(key_val_1==1) buffer<=16'h00ff; else buffer<=16'h0000; if(key_val_2==1) buffer<=16'h00f0; else buffer<=16'hf000; case(state) jiben: begin rs<=1'b0; data<=8'b00110000; state<=xianshi; end xianshi: begin data<=8'b00001100; state<=qingchu; end qingchu: begin data<=8'b00000001; state<=dizhi1; end dizhi1: begin rs<=0; data<=8'b10000000; state<=duanyu1; end duanyu1: begin rs<=1; case(buffer_bit) 0: begin data<=buffer[15]+8'h30; buffer_bit<=1;end 1: begin data<=buffer[14]+8'h30; buffer_bit<=2;end 2: begin data<=buffer[13]+8'h30; buffer_bit<=3;end 3: begin data<=buffer[12]+8'h30; buffer_bit<=4;end 4: begin data<=buffer[11]+8'h30; buffer_bit<=5;end 5: begin data<=buffer[10]+8'h30; buffer_bit<=6;end 6: begin data<=buffer[9]+8'h30; buffer_bit<=7;end 7: begin data<=buffer[8]+8'h30; buffer_bit<=8;end 8: begin data<=buffer[7]+8'h30; buffer_bit<=9;end 9: begin data<=buffer[6]+8'h30; buffer_bit<=10;end 10: begin data<=buffer[5]+8'h30; buffer_bit<=11;end 11: begin data<=buffer[4]+8'h30; buffer_bit<=12;end 12: begin data<=buffer[3]+8'h30; buffer_bit<=13;end 13: begin data<=buffer[2]+8'h30; buffer_bit<=14;end 14: begin data<=buffer[1]+8'h30; buffer_bit<=15;end 15: begin data<=buffer[0]+8'h30; buffer_bit<=0;state<=dizhi1;end endcase end idle: begin state<=idle; end endcase end endkey_scan key_scan_1( .sys_clk(sys_clk), .clr_n(clr_n), .key(key1), .key_val(key_val_1));key_scan key_scan_2( .sys_clk(sys_clk), .clr_n(clr_n), .key(key2), .key_val(key_val_2));endmodule /*//原始12位module xianshi(input sys_clk,input clr_n,input key1,input key2,input [11:0] buffer,output wire en,output reg rs,output wire rw,output reg [7:0] data);reg [16:0] count;reg clk ;reg f;assign en=f?1'b0:clk;assign rw=0;parameter jiben=8'b00000000, xianshi=8'b00000001, qingchu=8'b00000010, dizhi1=8'b00000011, duanyu1=8'b00000100, idle=8'b00000101;always @(posedge sys_clk or negedge clr) begin if(clr==1'b0) count<=17'b0; else begin count<=count+17'b1; if(count==17'b0) clk<=~clk; else ; endendalways@(posedge en or negedge clr_n )begin if(!clr_n) begin f<=0; state<=jiben; end else begin case(state) jiben: begin rs<=1'b0; data<=8'b00110000; state<=xianshi; end xianshi: begin data<=8'b00001100; state<=qingchu; end qingchu: begin data<=8'b00000001; state<=dizhi1; end dizhi1: begin data<=8'b10000000; state<=duanyu1; end duanyu1: begin rs<=1; case(buffer_bit) 0: begin data<=buffer[11]; buffer_bit<=1;end 1: begin data<=buffer[10]; buffer_bit<=2;end 2: begin data<=buffer[9]; buffer_bit<=3;end 3: begin data<=buffer[8]; buffer_bit<=4;end 4: begin data<=buffer[7]; buffer_bit<=5;end 5: begin data<=buffer[6]; buffer_bit<=6;end 6: begin data<=buffer[5]; buffer_bit<=7;end 7: begin data<=buffer[4]; buffer_bit<=8;end 8: begin data<=buffer[3]; buffer_bit<=9:end 9: begin data<=buffer[2]; buffer_bit<=10;end 10: begin data<=buffer[1]; buffer_bit<=11;end 11; begin data<=buffer[0]; buffer_bit<=0;end end idle: begin state<=idle; endendendmodule */并行lcd12864，当时写segama-delta adc时写的初稿
